Sr Staff Semiconductor Engineer, Physical Design (PnR)

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Sr Staff Semiconductor Engineer, Synthesis P&R Power Analysis

We are Aptiv - a global technology company with 190,000 specialists in 46 countries. We develop innovative software and build the hardware to bring autonomous driving cars, advanced driver-assistance systems, connected vehicles and smart cities to life in a way that only we can. We work in partnership with almost all car manufacturers. Our sensors, systems and software can already be found in almost all passenger cars today.

With our deep domain expertise, Aptiv is developing solutions that solve our customers' toughest challenges. We are enabling the transition to software-defined vehicles supported by electrified and intelligently connected architectures – which will combine to power the future of mobility.

Aptiv’s custom silicon management group provides critical custom Silicon for all Aptiv products including Autonomous Driving, ADAS, Infotainment, Zonal Control, and others. This team translates the system requirements of Aptiv’s next-generation products into the SOC/IC requirements and architectural design, then commissions external SOC/IC design partners to develop those products for Aptiv and manages the technical execution of the SOC/IC development.

We are looking for a Sr staff semiconductor design engineer to work closely with multiple Aptiv engineering teams who are focused on the development of Aptiv’s future generation of products.

This role is based in Aptiv’s Bangalore, India office and will interface closely with Aptiv teams in California, USA and Germany.  To facilitate collaboration with Aptiv’s US/EU teams this role’s regular working hours will include at least 7:30-10:30pm on workdays.

Your Role:

  • Drive the synthesis P&R and Power analysis and physical verification of various SOCs align it with the Aptiv product team and design partners.
  • Work with Aptiv Product architects and Design partner to Perform RTL Synthesis, P&R, Physical verification, Power analysis to achieve the best Performance/Power/Area of the designs.
  • Creating Power Intent for the designs and verify power intent on RTL, run static Low-Power checks on gate level netlists, Verify Logic Equivalency.
  • Checks between RTL to Gates and Gates to Gates, setup signoff
  • Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams.
  • Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows.
  • Implementation (PnR Signoff) of multimillion gate SoC designs in cutting edge process technologies (16nm, 7nm, 5nm)
  • Physical Design including Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM and DFY and Tapeout.
  • Push down the top-level floorplan and clock to Partition.IO Planning and bump planning.
  • Evaluate low power techniques and power reduction opportunities
  • Perform clock distribution design and analysis
  • Perform Physical verification activities at full-chip level.
  • Drive technical activities of physical design during technology readiness, design & execution
  • Innovate on the flows to meet the QOR targets and ensure predictability
  • exposure to the latest design rules, processes and innovations needed to close PPA on the advance nodes
  • Experience handling Netlist to GDS II at Chip level for multiple takeouts
  • Hands-on expertise with technology nodes like 7nm and below

Your Background:

  • Master degree in electrical engineering, computer engineering, or equivalent. 
  • 12+ years of experience in ARM CPU-based full-chip and subsystem SoC power aware synthesis, Timing closure
  • Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks.
  • Experience with Verilog and System Verilog RTL design experience with Perl/TCL/Makefile scripting.
  • Experience with Power Analysis using Power Artist and PTPX
  • Experience with full-chip static timing analysis through tape out, gate level simulations, and Functional ECO implementation with Automated flows.
  • Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company
  • Ability to work well in a team and be productive under tight schedules
  • Good knowledge of EDA tools from Synopsys, Cadence and Mentor, particularly with Innovus Calibre
  • Hands-on experience in Chip / block floor planning, placement optimizations, CTS and routing
  • Excellent understanding and hands on experience with Chip level physical verification (DRC/LVS/ERC/antenna) and other reliability checks (IR/EM/Xtalk)
  • Hands-on experience in block/top level signoff STA
  • Exposure in physical implementation of timing/functional ECOs
  • Excellent problem-solving and debugging skills.

Why join us?

  • You can grow at Aptiv. Whether you are working towards a promotion, stepping into leadership, considering a lateral career move, or simply expanding your network – you can do it here. Aptiv provides an inclusive work environment where all individuals can grow and develop, regardless of gender, ethnicity or beliefs.
  • You can have an impact. Safety is a core Aptiv value; we want a safer world for us and our children, one with: Zero fatalities, Zero injuries, Zero accidents.
  • You have support. Our team is our most valuable asset. We ensure you have the resources and support you need to take care of your family and your physical and mental health with a competitive health insurance package.

Your Benefits at Aptiv:

  • Hybrid and flexible working hours;
  • Higher Education Opportunities (UDACITY, UDEMY, COURSERA are available for your continuous growth and development);
  • Life  and accident insurance;
  • Sodexo cards for food and beverages
  • Well Being Program that includes regular workshops and networking events;
  • EAP Employee Assistance;
  • Access to fitness clubs (T&C apply);
  • Creche facility for working parents;

Apply today, and together let’s change tomorrow! 

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Aptiv is an equal employment opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, sex, gender identity, sexual orientation, disability status, protected veteran status or any other characteristic protected by law.

Organisation: 
Aptiv